June 4, 2015
EnSilica, a provider of semiconductor IP and services, has expanded its family of eSi-RISC processor cores with the addition of the eSI-32X0MP scalable, asymmetric multicore processor. This device is suited for applications that require a high level of processing per MHz and low power consumption in a small form factor.
The eSi-32X0MP’s PHY core offers advanced DSP acceleration with dual-MAC and SIMD instructions for complex arithmetic, various bit field operations and symbol level processing. It also implements both clock and power gating.
It is able to deliver up to 3.72 CoreMark per MHz. When optimized, it can be clocked at over 1GHz with a dynamic power of only 14.4µW/MHz per core.
“The eSi-32X0MP is ideal for implementing low-power Wi-Fi and wireless/cellular IoT standards such as LTE Cat-0,” said Ian Lankshear, CEO of EnSilica “The multicore architecture delivers exceptional processing performance at mature geometries. For example, an 180nm dual core configuration can deliver 500 MIPS for a gate count of less than 50k NAND equivalent gates.”
For more information, visit EnSilica.
Sources: Press materials received from the company and additional information gleaned from the company’s website.
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