January 24, 2020
Keysight Technologies, Inc. is unveiling a design and test workflow solution that reduces product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM) systems.
Keysight's design and test workflow solution enables hardware engineers to meet their time-to-market window and deliver an end-product with:
- new transmitter test methods to measure the signal eye diagram after equalization;
- new loopback bit-error-rate (BER) receiver tests to validate device and system reliability; and
- logic analysis to debug complex DDR5 traffic transactions to identify the source of system instability.
PathWave ADS Memory Designer for DDR5 is a simulation environment that addresses the current challenges faced by designers with the following key features:
- ability to predict performance, optimize a design and perform virtual transmitter compliance test, before realizing the first hardware prototype;
- reduced simulation setup time from hours to minutes with new features such as DDR components, smart wires and an intelligent memory probe and
- increased simulation accuracy for DDR5 by representing receiver equalization with IBIS Algorithmic Modeling Interface (IBIS-AMI) models, enhanced specifically for the requirements of DDR.
“DDR5 is on the horizon, and to secure a competitive edge, organizations are designing their next generation products to take full advantage of it,” says Todd Cutler, vice president and general manager of design and test software at Keysight. “However, designing for DDR5 will not be the step-and-repeat of earlier generations.
“The measurements needed to validate memory systems and the simulation technology needed to predict the performance of memory systems are evolving,” Cutler adds. “Keysight has the technical innovation, breadth of solution and depth of expertise to help our customers get to market faster with their first DDR5 product.”
Sources: Press materials received from the company and additional information gleaned from the company’s website.
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