NAND Flash Finds a Home in the IoT

The Internet of Things (IoT) presents design engineers with a new set of challenges. These range from the need for specialized operating systems to dealing with extreme constraints on power consumption and form factor.

As inherent as its demand for new processor architectures, the IoT also requires designers to deploy fast, flexible and inexpensive memory to address the challenges for data-heavy use cases. As a result, development teams have begun turning to a form of non-volatile memory (NVM) called NAND flash.

Developers usually relied on volatile memory for primary storage when the memory frequently interacted with a system-on-a-chip, a practice that relegated NVM to secondary/mass storage applications. This rule of thumb, however, appears to be changing.

Advances in the technology now let NAND flash memory offer faster throughput, greater flexibility and better price points per byte, opening the door for its use as primary storage. All of these factors seem to be positioning the technology as a competitive option for IoT applications involving the collection and analysis of mass data pools.

Density vs. Endurance

NAND flash memory comes in various formats, defined by the number of bits that can be stored in a single cell. For example, a single-level cell stores 1 bit of data; multilevel cells (MLC) can store more than a single bit of information. The market also offers triple-level (TLC) and quad-level cells. Pushing the technology to the next level, chipmakers have begun offering 3D NAND devices in MLC and TLC formats. These new architectures stack storage elements in as many as 96 layers, offering capacities ranging from 128 MB to 2 TB.

NAND flash technology offers designers a number of density options, which enable developers to tailor their designs to meet application requirements. Trade-offs come into play, however, when designers try to strike the right balance between cell endurance and cell density. Here, the guiding rule of thumb is that the higher the cell’s density, the lower its endurance.

The Problem with Frequent and Random Writes

Although NAND flash technology’s flexibility and ability to handle data-heavy IoT applications holds great appeal, engineers also must factor its limitations into design deliberations. One such issue involves the frequency and manner in which users access and read/write data to memory. These factors impact NAND devices’ endurance.

The underlying factor is that NAND flash differs from other memory technologies in that users cannot reprogram or write data to NAND devices at the individual byte level. The technology’s architecture dictates that the storage elements be read and programmed only in pages. At the same time, these storage devices can be erased only in blocks. During this process, the block must be completely erased before it can be reprogrammed.

Because of the way these processes work, the engineer must be aware of the types of data in play, the order in which the data is read and the frequency that writes occur.

For example, log files captured from sensors can be numerous and are typically read/written in no particular order. Frequent and random writing of small data files reduces endurance and can eventually lead to failure.

A countermeasure for this condition is wear leveling. This evens out the erase count of all blocks, essentially leveling the wear across the entire flash storage device and extending its life expectancy.

Avoiding Data Loss

Overwriting, moving and deleting data are not the only operations that can give designers headaches. The frequent reading of memory block data can trigger threshold voltages in unread cells in the same block that shift the data to different logical states. These read disturb errors can cause data loss if the errors exceed the error-correcting code (ECC) threshold.

Fortunately, high-grade NAND flash memory typically includes read leveling and ECC that mitigates these problems.

NAND developers aim to extend its advantages by further reducing the cost per bit and increasing maximum chip capacity. They hope to make flash memory competitive with magnetic storage devices like hard disks.