Cadence Expands System VIP Portfolio

Goal is to to accelerate automotive, hyperscale data center and mobile system-on-a-chip verification.

Goal is to to accelerate automotive, hyperscale data center and mobile system-on-a-chip verification.

Cadence Design Systems, Inc. makes available 13 new verification IP (VIP) solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols. The new Cadence VIP offerings enable customers to develop next-generation automotive, hyperscale data center and mobile systems on a chip and microcontrollers while meeting industry standards, including Arm AMBA 5 CHI-f, Universal Chiplet Interconnect Express (UCIe), GDDR7, DDR5 DIMM, MIPI A-PHY and SoundWire I3S and USB4 2.0 interfaces.

The new Cadence VIP offer customers a verification solution for complex protocols. Cadence customers have access to a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications, including:

Hyperscale data center:

  • UCIe
  • AMBA 5 CHI-f
  • DTI
  • Latest version of DDR5 DIMM


  • MIPI A-PHY 1.1
  • CAN XL
  • Flash ONFI 5.1

Consumer and mobile:

  • USB4 2.0
  • GDDR7
  • MIPI SoundWire I3S (SWI3S)
  • Latest version of LPDDR
  • DFI
  • HDMI 2.1

All Cadence VIP solutions include Cadence TripleCheck technology, which provides users with a specification-compliant verification plan linked to coverage models and a test suite to ensure compliance with the interface specification. The new VIP also supports the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis and data and cache coherency checkers. Using the expanded System VIP portfolio, customers can experience efficiency improvements.

“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” says Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio, and the Verisium AI-Driven Verification Platform. The VIP solutions and verification full flow support the company’s Intelligent System Design strategy. For more information, click here.

Sources: Press materials received from the company and additional information gleaned from the company’s website.

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