Cadence, TSMC Work Together to Advance Design of AI Silicon

Cadence reports an expansion of its relationship with TSMC to enhance AI-driven semiconductor development. The expanded collaboration will deliver IP, signoff-ready, end-to-end design infrastructure, and advanced, certified flows for AI silicon on TSMC’s N3, N2, A16 and A14 process technologies.

The companies’ work will help reduce iterations and improve correlation for design technology co-optimization-focused advanced AI and high-performance computing designs. 

“AI silicon innovation at advanced nodes demands a signoff-ready approach that spans the full design cycle and scales from SoCs to chiplet and 3D-IC architectures,” says Chin-Chi Teng, senior vice president and general manager, Cadence. “Through collaboration with TSMC, we’re advancing our Design for AI and AI for Design strategy by uniting certified flows with silicon-proven IP and building the agent-ready foundation that will help engineers improve productivity as complexity continues to rise.”

"The growing demands of AI compute workloads, combined with compressed design cycles, require advanced, energy-efficient silicon technologies, streamlined design flows, and silicon-validated IPs," says Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC. "Through our collaboration with Open Innovation Platform (OIP) ecosystem partners like Cadence, we empower customers to confidently design cutting-edge silicon using TSMC’s latest process technologies and 3DFabric® advanced packaging solutions—unlocking transformative opportunities for AI-driven innovation."

Design for AI

Cadence is delivering an IP portfolio for TSMC N2P, including DDR5 12.8G MRDIMM, PCIe 6.0, LPDDR6/5X 14.4G and HBM4E 16G. The Cadence Artisan foundation IP advanced-node portfolio is now in production designs using TSMC N3 process technologies.

Cadence enables semiconductor teams with certified, end-to-end EDA flows that scale from advanced-node SoCs to chiplet and 3D-IC designs, including implementation with the Innovus Implementation System; custom/analog implementation and simulation with Virtuoso Studio and the Spectre Simulation Platform; thermal analysis with the Celsius Thermal Solver, Voltus IC Power Integrity Solution, and EMX Planar 3D Solver; and signoff technologies with Tempus Timing and ECO Solution, Quantus Extraction Solution, Liberate Characterization Portfolio, and Pegasus Verification System; all certified for TSMC N2 and A16, and ongoing collaboration for A14 PDKs.​​ Additionally, the Genus Synthesis Solution is enabled for these process technologies and ongoing collaboration on Clarity 3D Solver.

For 3D-IC and heterogeneous integration, the Cadence Integrity 3D-IC Platform supports the TSMC-COUPE Reference Flow for stacked-die, while Virtuoso Studio’s heterogeneous integration methodology adds silicon photonics support. Celsius thermal-aware flow is enabled including PIC placement with Virtuoso and signal integrity analysis with EMX. 

AI for Design

Cadence’s agentic AI shifts EDA from tool-by-tool workflows to goal-driven, agentic execution. Working with TSMC, Cadence is preparing “agent-ready” design flows, optimization engines, and signoff infrastructure.

The enhanced Genus Synthesis Solution, Innovus Implementation System, and Cadence Cerebrus Intelligent Chip Explorer’s AI-driven implementation is optimized to support TSMC NanoFlex Pro standard cell architecture for DTCO. In addition, front-end placement and back-end routing rules improve correlation between pre-route and post-route results; and TSMC’s A16 Super Power Rail enables denser and faster designs by routing power nets on the backside of the chip.​

In custom design, Cadence has embedded agentic AI in Virtuoso Studio flows with circuit optimization for TSMC process technologies. This includes the enablement for N2-to-A14 Analog Design Migration flow.​

Sources: Press materials received from the company and additional information gleaned from the company’s website.