Cadence and Samsung Foundry Deepen Collaboration

Cadence and Samsung Foundry report development of a full portfolio of Memory and Interface IP, and expanded certification of Cadence’s agentic AI digital, custom, 3D‑IC and system design and analysis (SDA) flows for Samsung Foundry’s 2nd-gen 2nm process technology.

This collaboration delivers a signoff‑ready platform for next‑generation AI infrastructure and physical AI designs across data center, edge and intelligent devices. 

Building on the companies’ 2025 announcement of certified Cadence tools and IP on multiple Samsung Foundry nodes, including 2nd-gen 2nm, this new multi-year agreement further broadens the Cadence portfolio of Memory and Interface IP, including NVIDIA NVLink-C2C-enabled interconnect and CUDA-X GPU-accelerated libraries spanning high-speed SerDes, PCIe, UCIe and all leading memory interfaces on 2nd-gen 2nm. 

“AI infrastructure and physical AI are pushing the industry into advanced node and 3D‑IC designs that demand far more capacity, integration and signoff confidence than ever before,” says Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. 

“Customers are increasingly drawn to Samsung Foundry’s second-generation 2nm for leading‑edge AI designs that must keep pace with the exploding demand across AI infrastructure and emerging physical AI applications,” said Jongshin Shin, executive vice president and head of Foundry Design Platform Development at Samsung Electronics. “Our expanded Cadence partnership delivers a robust semiconductor and 3D-IC platform with advanced Memory, Interface IP and AI-optimized flows for superior performance, efficiency and innovation.” 

Agentic AI EDA/SDA Platform and 3D-IC Design 

Cadence and Samsung Foundry deliver a certified flow on 2nd-gen 2nm, including Cadence’s Innovus Implementation System for digital implementation, Virtuoso Studio for analog and custom design, Integrity 3D‑IC Platform for full 3D‑IC system planning and implementation, Voltus IC Power Integrity Solution for power integrity and system‑level power analysis, and Quantus Extraction Solution and Tempus Timing Solution for signoff. 

Samsung 3D Cube-H design is enabled with a full system planning, implementation and signoff flow for hybrid copper bonding (HCB) technology, including Cadence Cerebrus Intelligent Chip Explorer, Integrity 3D‑IC, Innovus Implementation, Voltus IC Power Integrity (ERA) and Pegasus Verification System. 

Advancing NVLink-C2C Interconnect 

NVIDIA is leveraging Cadence and Samsung Foundry’s expanded advanced-node and 3D-IC platform to deliver high-bandwidth interconnect through NVIDIA NVLink-C2C and CUDA-X GPU accelerated capabilities. 

Enabling Ambarella’s Edge AI Platform 

Ambarella is developing its 2nm edge AI platform for ultra-low-power AI perception and physical AI SoCs for intelligent edge systems spanning robotics, drones, autonomous machines, and advanced sensing applications. 

Sources: Press materials received from the company and additional information gleaned from the company’s website.