Moving Forward with AWG-Based Testing for MIPI PHYs

By Keyur Diwan, Tektronix

Receiver testing for MIPI standards has always been a challenge for engineers and test equipment manufacturers. Fortunately, as technologies have evolved, the choice of test and measurement equipment has expanded to keep pace.

The MIPI Alliance’s first PHY, D-PHY, has had wide industry adoption for about 10 years now. With D-PHY as the starting point, MIPI standards have continued to evolve with an emphasis on application based PHYs and providing more choices for the mobile community to implement PHYs based on consumer use cases and the market being served. For example, C-PHY is a choice for high-end cameras, while D-PHY is used for camera and display. M-PHY continues to drive storage applications, like UFS.

Along with adding new PHYs, MIPI has evolved its specifications over time to meet market needs for higher data rates, low power and increased performance. Today D-PHY operates up to 4.5Gbps compared to 500Mbps when it started 10 years ago. M-PHY runs all the way up to 11.6Gb/s and C-PHY goes up to 3GS/s.

As the specifications have evolved, so have the needs for testing them. Some of the typical test and measurement challenges that engineers are facing include increased complexity in physical setup, maintenance of the setup, inability to generate a variety of stresses and the ability to generate various encoded patterns, all with the exact amount of jitter each time. For MIPI receiver testing the use of arbitrary waveform generator (AWG) technology is gaining momentum, especially for D-PHY and C-PHY due to the cost and time savings afforded by AWGs.

While there are AWGs with sufficient performance readily available in the market, MIPI receiver test needs for D-PHY and C-PHY call for updates to the requirements in terms of signal or stress generation, putting specific constraints on AWGs. This is an area worth looking at more closely. These constraints include the following:

• Channel Sample Rate: The D-PHY 2.0 spec is currently at a data rate of 4.5Gb/s. C-PHY is at 3GS/s and expected to match D-PHY in future revisions. The need for AWG sample rate is determined based on the conservative 4 SPUI calibration approach. So, to support a data rate of 4.5Gb/s for D-PHY, you need a channel sample rate of 18GS/Channel (channel sample rate = data rate x SPUI). Future data rates of C-PHY, if they reach 4.5GS/s, would have a similar requirement.Given the AWGs available on the market today, a typical test setup would include two synchronized AWGs. Some of the AWGs available may be able to support current C-PHY data rates in a single chassis. However, the setup does not scale for future data rates of C-PHY and would not support the current version of the D-PHY spec in a single AWG with 4-channels. Therefore, a 2-channel AWG with sample rates of about 25GS/channel will soon be needed. To future proof investments, designers and engineering managers need to think about their setups and how they scale to meet the future needs of these evolving technologies.

• Memory Depth per Channel (Extended Memory): C-PHY and D-PHY support many pseudo random patterns including PRBS18. With a 4 SPUI as a rule of thumb, you need memory depth of more than 1 M samples per channel. This is typically sufficient for compliance. However, for margin testing of many receiver designs, engineers will need greater memory depth. For these cases a typical memory depth of 2 M samples per channel will suffice.

• Switching Jitter: A certain amount of jitter is inherent in three wires and three levels of C-PHY signaling. This is referred to as the switching jitter. Simulation results show that C-PHY signaling introduces a switching jitter for 0.1 UI. This implies that the signals generated from test equipment (typically AWGs) for receiver testing should not introduce switching jitter more than 0.1 UI. Users need to make an educated choice of these generators especially for characterization of devices. Exceeding switching jitter will eat into the total jitter budget, which could prevent you from making accurate margin testing of device under test.

• Signal to Noise Ratio and Precision Stress Control: Vertical resolution of 8 bits or more is needed to have a good signal-to-noise ratio (SNR) and accurately generate the quantum of jitter or stress. Such granularity of resolution such as 8 bit, 9 bit or 10 bits of the DAC is highly recommended, especially when you are looking at testing technologies, like C-PHY and D-PHY. A poor resolution signal with low SNR can result in non-monotonic signals being generated or a glitch. This can result in wrong clock recovery, increased switching jitter and corrupted data being transmitted.

For C-PHY and D-PHY the industry is quickly migrating to error detectors built into the chips (iBER). Most of the test companies provide a mechanism to read this iBER register from the chip, typically over a JTAG interface with some form of script. An AWG does not have the ability to read or count any errors, but it can interface via software scripts with the chips over an interface. An AWG can also read register values and count errors. No loopback mechanism is described in the spec for C-PHY or D-PHY receiver implementation.

AWGs utilize direct synthesis methods for waveform generation and add different impairments with precise control, which is a challenge for many other types of generators. A few of the examples of signal generation and stresses required for D-PHY and C-PHY include spread spectrum clocking, dynamic skew, duty cycle distortion, ISI channel effects, de-emphasis, sinusoidal disturber signal, eSpike and more. The ability to generate de-emphasis, SSC, impairments such as DCD and skew, are recommended for calibration procedure for these PHYs as per the CTS. Figure 1 shows a screen capture of eSpike on a calibrated eye for C-PHY using the stresses as per the CTS. Figure 2 shows a calibrated D-PHY eye diagram.

An AWG provides much finer control, granularity and repeatability in terms of the signals and stresses being generated. It has the ability to generate a variety of different waveforms that support LP-HS transition for C-PHY and D-PHY, even with different startup sequences and sequencing on-the-fly. All these waveforms can also generate thousands of different test scenarios.

Additionally, the “sequencing” ability of the AWG allows you to sweep through a wide range of voltage values and stresses. It can generate multiple waveforms and sequence them so that they emulate the effect of turning the knob to dial in jitter. With the help of AWGs, it’s possible to save all these waveforms, use them offline and share them with teams globally. This helps with isolation of bugs early in the development cycle for globally dispersed teams.

Spec Evolution’s Impact

There are ongoing discussions in the industry about even higher data rates for D-PHY and C-PHY. If these PHYs were to get close to M-PHY in terms of data rate, 11.6Gb/s, then the current AWGs available in the industry would fall short in terms of resolution and channel sample rate. Even a 6Gb/s D-PHY would require a channel sample rate of 25Gb/s per channel of output from a single channel of the AWG.

For C-PHY and D-PHY, the industry has moved from traditional generators to AWG-based testing. If enough thought is not put into the design of the new MIPI specs, we may have to move the industry to yet another instrument for future data rates. Industry experts need to have a holistic approach to designing the new specifications so that the existing test equipment can be reused and specifications evolved with consideration for the entire ecosystem.

However, if market needs lead to specifications with higher data rates, we may not have a choice but to explore new ways of redesigning existing equipment to meet the test and measurement needs of the industry or look at alternative equipment to enable new designs.

Keyur Diwan is a product marketing manager at Tektronix. Send email about this commentary to DE-Editorsmailto:[email protected].