Synopsys Accelerates AI and Multi-Die Design Innovation

Synopsys, Inc. reports its ongoing close collaboration with Samsung Foundry to power the next generation of designs for advanced edge AI, high-performance computing and AI applications.

The collaboration between the companies is helping customers achieve tape-outs of their complex designs using Synopsys' 3DIC Compiler and Samsung's advanced packaging technologies with fast turnaround time. Mutual customers can improve power, performance and area (PPA) with certified EDA flows for SF2P process, and minimize IP integration risk with the portfolio of IP on Samsung's process technologies.  

"The adoption of Edge AI applications is driving the need for advancements in semiconductor technologies to enable complex computational tasks, improve efficiency, and expand AI capabilities across various industries and applications," says John Koeter, senior vice president for the Synopsys IP Group. "Together with Samsung Foundry, we're enabling the most advanced AI processors across a broad spectrum of use cases from high-performance AI inference engines for data centers to ultra-efficient Edge AI devices like cameras and drones, all optimized for development on sub-2nm Samsung Foundry process technologies."

"Synopsys and Samsung have deepened their collaboration to optimize PPA for designs using Samsung's advanced technologies," says Hyung-Ock Kim, vice president and head of the Foundry Design Technology Team at Samsung Electronics "With Synopsys' AI-driven design flows certified for Samsung's SF2 and SF2P processes, customers can seamlessly integrate these solutions into their workflows. This collaboration also provides access to Synopsys' broad portfolio of IP optimized for Samsung's advanced nodes. Additionally, our joint efforts in delivering multi-die solutions, including 2.5D automated routing with Synopsys' 3DIC Compiler and Samsung's I-CubeS™ technology, are pushing the boundaries of innovation in this domain."

Synopsys and Samsung are powering complex multi-die designs. The companies' most recent collaboration includes a tape-out of a customer design using Synopsys' 3DIC Compiler, a unified exploration-to-signoff platform, and Samsung's I-CubeS 2.5D packaging technology, which allows several HBM stacked dies on a silicon interposer.

In addition to reducing HBM routing time to 4 hours, the Synopsys 3DIC Compiler improved worst-case eye opening by 6% for better performance and reliability. The ongoing projects leverage 3DIC Compiler's 3D floorplanning with bump and Through-silicon via (TSV) planning and early thermal analysis, which is certified by Samsung for Samsung's X-Cube technology.

Collaboration on Design Technology 

Synopsys and Samsung Foundry have had a collaboration using AI-driven design technology co-optimization (DTCO) to achieve PPA entitlement on SF2 and SF2P processes. Synopsys and Samsung also continue to collaborate on AI-driven flows using Synopsys ASO.ai™, resulting in a new schematic migration flow to efficiently migrate Samsung SF4 analog IPs to the SF2 process. 

In addition, Synopsys' AI-driven digital and analog flows have achieved certification on Samsung Foundry's SF2P process with hypercells enablement for use of standard cell space, improving overall PPA, along with certified digital and analog flows for SF2/SF2P generation nodes. The flows, powered by the Synopsys.ai full-stack EDA suite, allow mutual customers to accelerate development of differentiated SoCs on Samsung's advanced process technologies.

Sources: Press materials received from the company and additional information gleaned from the company’s website.