Synopsys Unveils Software-Defined Hardware-Assisted Verification Capabilities

Synopsys shares advancements across its hardware-assisted verification (HAV) portfolio, including new hardware platforms and capabilities to support AI chip verification from the data center to the edge. Synopsys HAV platforms, powered by the company's software-defined capabilities, set scalability and use case benchmarks for verifying multi-die and AI chips.

"As AI-driven systems become more complex, verification must scale just as quickly. Hardware-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness," says Salil Raje, senior vice president and general manager, Adaptive and Embedded Computing Group, AMD. "FPGA-based emulation and prototyping play a central role in that effort by accelerating system bring-up and enabling earlier software development. Our collaboration with Synopsys reflects that focus. Through joint optimization of Synopsys ZeBu with the AMD Vivado software stack, and by leveraging AMD EPYC processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster."

"As AI becomes more pervasive across almost every industry and products are now workload-optimized and silicon-powered, building high confidence early that the workloads are running to spec on the silicon under development is critical," says Ravi Subramanian, chief product management officer at Synopsys. "Our software-defined, hardware-assisted verification solutions deliver continuous innovation. They are a powerful force multiplier to scale verification productivity and meet the growing demand for pre-silicon development across industries."

The latest advancements across Synopsys' software-defined hardware-assisted verification portfolio, include:

Breakthrough performance and capacity for the AI era: The latest software-defined updates and modular HAV are available across the ZeBu and HAPS platforms. Of note, with these updates, ZeBu Server 5, supports complex designs to meet the demands of mega designs supporting data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads. 

New HAPS and ZeBu platforms: The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address high-performance requirements for data center-sub-system, mobile, client, server, consumer, and edge AI applications. Synopsys also introduces the new HAPS-200 1 FPGA platform as a desktop system for IP verification and software bring-up using Synopsys Interface Prototyping Kits.

Software-defined HAV capabilities extend system lifetime value: The Synopsys HAV portfolio supports new, industry-first Hardware-Assisted Test Solutions, test automation capabilities that allow teams to stress corner cases for processor, memory, and I/O subsystems as well as full-system coherency validation and observe system behavior under realistic workloads in emulation long before silicon is ready. For mixed-signal and system-level designs, Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior within digital-centric verification flows for faster software bring-up. 

Availability & Additional Resources
Software-defined enhancements are being rolled out continuously across the HAV portfolio, with the new capabilities available to users now. The new EP‑Ready HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms are available today and in Q3 2026, respectively. HAPS-200 1 FPGA platform is available today.

• Product Page: Synopsys HAV Solutions Family   
• Video: Software-Defined Hardware-Assisted Verification for the AI Era

Sources: Press materials received from the company and additional information gleaned from the company’s website.