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The Digital Autonomy with RISC-V in Europe, Special Grant Agreement 1 (DARE SGA1) project is officially launching the first phase of an initiative to enhance Europe’s technological advanves in high-performance computing (HPC) and artificial intelligence (AI). Supported by the EuroHPC Joint Undertaking, and coordinated by the Barcelona Supercomputing Center (BSC-CNS), DARE SGA1 unites 38 leading partners from across Europe to develop next-generation European processors and computing systems, including an optimized software ecosystem, designed for research and industry applications.
"I am proud to announce the launch of the DARE project which marks a significant milestone for European digital sovereignty," says Anders Jensen, EuroHPC JU Executive Director. "This ambitious initiative will drive innovation in both hardware and software technologies and leverage the full power of HPC and AI to develop secure, efficient, and European-led solutions for the future."
With a first phase budget of €240 million, this 3-year project marks the first phase of a 6-year DARE initiative. DARE SGA1 is set to build a fully European supercomputing hardware (HW)/software (SW) stack for HPC and AI, featuring high-performance and energy-efficient processors designed and developed in Europe. The initiative is reportedly a direct response to Europe’s strategic need for digital sovereignty.
Europe has long been dependent on non-European HW and SW solutions for its supercomputing infrastructure, according to the project leaders. This reliance poses risks to security, economic stability, and technological competitiveness, experts say. DARE SGA1 seeks to reverse this trend by leveraging the open RISC-V ecosystem, and the latest chiplet technology, creating European products that will power Europe’s future supercomputers.
Click here for a full-size project map.
At the heart of the DARE SGA1 project is the development of three RISC-V-based chiplets, each serving a role in HPC and AI computing:
These chiplets will be developed and taped-out in advanced CMOS technology nodes.
DARE SGA1 employs a HW/SW co-design approach, using a set of European HPC and AI applications to guide development. A complete SW stack, optimized for DARE SGA1 HW, will be built in parallel with HW design, leveraging early access to RISC-V HW emulation and simulation. Additionally, DARE will include exploratory pathfinding SW and HW design activities for the immediate future and roadmapping efforts to conduct scalability studies for future supercomputer deployments.
In addition to the previously mentioned Openchip, Axelera AI, and Codasip, imec and JÜLICH SUPERCOMPUTING CENTRE (JSC) at FORSCHUNGSZENTRUM JÜLICH will serve as technical leads. Besides being overall coordinator, BSC will also lead roadmapping as well as the VEC pathfinding efforts.
By the end of its first phase, DARE SGA1 will lay the groundwork for Europe’s first fully European HPC system, fostering technological self-reliance and ensuring that European industry, research, and society at large can benefit from secure, high-performance, and energy-efficient computing solutions.
DARE SGA1 is intended to define the roadmap for Europe’s post-exascale supercomputers. The project will pave the way for future generations of supercomputers that are designed, built, and optimized in Europe, ensuring that Europe remains at the forefront of HPC and AI development and use.
Digital Autonomy with RISC-V in Europe (DARE SGA1) is a large-scale European supercomputing project that has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 101202459. DARE SGA1 aims to develop prototype HPC and AI systems based on EU-designed and developed industry-standard chiplets.
For more information visit DARE website or contact [email protected]
Sources: Press materials received from the company and additional information gleaned from the company’s website.
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