Siemens unveils Calibre DesignEnhancer

Product designed for Calibre correct-by-construction integrated circuit layout optimization.

Product designed for Calibre correct-by-construction integrated circuit layout optimization.

Design solution enables integrated circuit (IC), place-and-route (P&R) and full-custom design teams to improve productivity. Image courtesy of Siemens.

Siemens Digital Industries Software introduces Calibre DesignEnhancer software, a solution that enables integrated circuit (IC), place-and-route (P&R) and full-custom design teams to improve productivity, boost design quality and reduce time to market by automatically implementing ‘Calibre correct-by-construction’ design layout modifications earlier in the IC design and verification process.

The latest in a series of “shift left” tools for Siemens’ Calibre nmPlatform for IC physical verification, the new Calibre DesignEnhancer tool helps enhance physical verification readiness by optimizing designs to reduce or eliminate voltage (IR) drop and electromigration (EM) issues. 

With Siemens’ new Calibre DesignEnhancer tool, design teams can shorten turnaround time and reduce EM/IR issues while preparing a layout for physical verification, the company reports.

The Calibre DesignEnhancer tool currently provides three use models:

Via modification automatically analyzes layouts and inserts up to 1 million+ Calibre-clean correct-by-construction vias to reduce the impact of via resistance on EM/IR and reliability. Because these modifications are based on understanding of the layout and signoff design rules, via insertion can help customers meet power goals without impacting performance or area metrics, according to Siemens.

Power/ground enhancement automatically analyzes layouts and inserts Calibre nmDRC-clean vias and interconnects in open tracks to create parallel runs that can lower resistance on power/ground structures and reduce IR and EM issues associated with the power grid. 

Filler cell insertion optimizes the insertion of decoupling capacitor (DCAP) and filler cells required for physical verification readiness. It replaces traditional P&R filler cell insertion processes.

“In today’s challenging IC design environment, engineering teams working at advanced nodes are struggling to optimize layouts for manufacturability and performance within the given area and project timeline constraints in which they must work,” says Michael White, senior director, Physical Verification Product Management, Calibre Design Solutions, Siemens Digital Industries Software. “By using the Calibre DesignEnhancer software, designers can bring Calibre polygonal processing speed and accuracy into play earlier in the design cycle, which can help to avoid late design cycle surprises.”

The Calibre DesignEnhancer solution uses technology, engines, and qualified rule decks from Calibre, which can help generate results that are correct by construction, Calibre DRC-clean and ready for signoff verification. It can read OASIS, GDS and LEF/DEF as input files, and output layout modifications in any combination of OASIS, GDS, or incremental DEF files, helping design teams to back-annotate Calibre DesignEnhancer software changes to the design database for power and timing analysis using commonly preferred tools for analysis earlier in the design creation lifecycle.

The Calibre DesignEnhancer tool integrates with all major design and implementation environments using industry interface standards, providing a user-friendly environment requiring minimal training and setup. Calibre DesignEnhancer kits are available now for all foundries supporting designs from 130nm to 2nm, depending on the use model and the technology. For more information about the Calibre DesignEnhancer tool, click here. 

Sources: Press materials received from the company and additional information gleaned from the company’s website.

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