EMA TimingDesigner 9.1 Adds SDC Support and Integration with Altera's Quartus II Software

By DE Editors

EMA Design Automation (Rochester, NY), a full-service provider of Electronic Design Automation (EDA) solutions, announced TimingDesigner version 9.1, adding support for SDC, which provides the ability to interface with FPGA and ASIC design flows.

TimingDesigner is the industry standard tool for interface timing design. It provides an easy to use and intuitive method for defining and analyzing interface-timing requirements. The introduction of version 9.1 makes TimingDesigner the only tool that can generate SDC timing constraints from a timing diagram. This enables users to visually define design requirements and then automatically generate SDC to drive place and route.

Generating SDC directly from a timing diagram removes any confusion as to the intent behind the constraints and allows users to visually debug and refine their SDC with ease. It also greatly reduces the learning curve for users new to the SDC format.

The initial release of TimingDesigner with SDC support focuses on the Altera FPGA design flow.

TimingDesigner 9.1 (starts at $2,995) includes a number of general productivity enhancements and updates as part of the ongoing efforts to provide the highest quality timing analysis software on the market. It will be available at the end of October and is free to existing customers with a valid maintenance contract.

For more information on TimingDesigner 9.1, visit EMA Design Automation, Inc.

Sources: Press materials received from the company and additional information gleaned from the company’s website.